1. Field of the Invention
The present invention relates to a method for forming a bit-line of a semiconductor device, and more specifically, to a method for forming a bit-line of a semiconductor device having low bit-line capacitance. In a line patterning process for forming a bit-line in a DRAM (Dynamic Random Access Memory) of a semiconductor device, a barrier metal layer and a tungsten layer are sequentially formed on an interlayer insulating film comprising a contact hole to fill the contact hole by a CVD (Chemical Vapor Deposition) method. Then, the barrier metal layer and the tungsten layer are removed until the interlayer insulating film is exposed, and a tungsten layer having small thickness is re-formed on the exposed interlayer insulating film by a PVD (physical Vapor Deposition) method. As a result, the bit-line area is reduced as much as the barrier metal layer removed from the upper portion of the interlayer insulating film, thereby having low bit-line capacitance.
2. Description of the Prior Art
Due to high integration and high capacity of semiconductor devices, capacity of a DRAM device increases with increase of the number of charged and discharged bits. However, the cell size of semiconductor devices is decreased, and it is difficult to obtain sufficient capacitance necessary for operation of the device. The capacitance C is proportional to the dielectric constant ε and the storage electrode surface area A, and is inversely proportional to the thickness d of the dielectric film as follow Equation 1.
                    C        =                  ɛ          ⁢                      A            d                                              [                  Equation          ⁢                                          ⁢          1                ]            
If the capacitance of the device is not secured, coupling capacitance of various wires for forming a cell array increases, and the subsequent sensing margin of a sense amplifier decreases. Therefore, the capacitance is secured by using a method of increasing the cell capacitance Cs or decreasing the bit-line capacitance Cb.
However, to use the method of increasing the cell capacitance, a dielectric material having a large dielectric constant is used or a cap oxide film having a thick thickness is formed. As a result, wires of bit-line are formed of tungsten and TiN having low resistance to decrease the capacitance of the bit-line. However, since it is difficult to effectively reduce the capacitance of the bit-line using the above-described method, studies have been made to solve the problem.
FIGS. 1a to 1d are cross-sectional diagrams illustrating a conventional method for forming a bit-line of semiconductor.
Referring to FIG. 1a, a polysilicon layer (not shown), a conductive layer for gate electrode (not shown) and a hard mask nitride film (not shown) are sequentially formed on a semiconductor substrate 1 comprising a device isolation film 2.
A selective etching process is performed on the hard mask nitride film (not shown), the conductive layer for gate electrode (not shown) and the polysilicon layer (not shown). A gate line 6 where a polysilicon pattern 3, a conductive layer for gate electrode 4 and a hard mask nitride film pattern 5 are sequentially stacked is formed.
As shown in FIG. 1b, an interlayer insulating film (not shown) is formed on the semiconductor substrate including the gate line 6 of FIG. 1a. Then, the selective etching process is performed until the upper surface of the hard mask nitride film pattern 5 and the semiconductor substrate 1 to form an interlayer insulating film pattern 8 having a bit-line contact hole 10 of a cell region and a bit-line contact hole 12 of a peripheral circuit region.
As shown in FIG. 1c, a barrier metal layer 14 using Ti/TiN and a CVD tungsten layer 16 are sequentially formed on the semiconductor substrate including the bit-line contact holes 10 and 12 of FIG. 1b. 
The barrier metal layer 14 has a thickness ranging from 100 to 200 Å, and the CVD tungsten layer has a thickness of less than 1000 Å.
A photoresist pattern 18 is formed on the upper surface of the CVD tungsten layer 16 of FIG. 1c via an exposure and developing process. Then, as shown in FIG. 1d, the CVD tungsten layer is etched using the photoresist pattern 18 as an etching mask to form a CVD tungsten pattern 16-1.
However, since the barrier metal layer as conductor for bit line and the CVD tungsten layer are stacked at the small thickness on the upper surface of the interlayer insulating film, the area of bit-line becomes larger and capacitance becomes higher in subsequent formation of a capacitor, thereby decreasing the sensing margin of the subsequent DRAM operation.